Semichrony  Design Optimizer helps you achieve better synthesis results of smaller silicon area and reduced clock cycle time. For a RISC-V Rocket chip processor at 45nm, compared with the minimum cost design synthesized by Synopsys Design Compiler, the minimum cost design achieved by applying both Semichrony Design Optimizer and Synopsys Design Compiler is 5.3% smaller and 12.5% faster (shown by the red arrow in the figure); at the minimum cost achieved by Synopsys Design Compiler, applying both Semichrony Design Optimizer and Synopsys Design Compiler achieves more than 35% clock cycle time reduction (shown by the purple arrow in the figure). For a SPARC V architecture LEON2 processor at 45nm, compared with the minimum cost design synthesized by Synopsys Design Compiler, the minimum cost design achieved by applying both Semichrony Design Optimizer and Synopsys Design Compiler is 9.1% smaller and 10.0% faster; at the minimum cost achieved by Synopsys Design Compiler, applying both Semichrony Design Optimizer and Synopsys Design Compiler achieves more than 33% clock cycle time reduction, or more than 50% clock frequency boost.

In technology scaling, while the nominal value of a parameter is scaled down, the percentage of variation increases. This leads to diminished performance scaling in the traditional synchronous IC design methodology wherein the critical path delay must not exceed the clock cycle time. Alternatively, better-than-worst-case VLSI design allows the worst-case signal propagation path delay to exceed the clock cycle time, which does not compromise logic correctness if any timing error is predicted or detected, and a timing error avoidance or recovery scheme is present. Further, because most timing-critical paths have a tiny probability for a signal to propagate through it, overall performance improvement is achievable for a better-that-worst-case design with a timing error avoidance/recovery scheme. We achieve minimum-cost better-than-worst-case VLSI design by predicting a timing error occurrence based on the side-inputs of a timing-critical path which must take respective non-controlling logic values for a signal to propagate through the timing-critical path. For a SPARC V architecture LEON2 processor integer unit at 45nm, this technique leads to ~40% performance improvement at virtually no cost in energy consumption and silicon area. We published this technique in a journal article with Intel Labs.

Timing error detection complements timing error prediction by capturing timing errors which are either unpredictable, e.g., due to runtime uncertainties, or hard-to-predict, e.g., due to limited accuracy in characterization or prediction. We have developed a timing error detecting element which detects all timing error occurrences and is free of any false alarm. This leads to a completely timing error-resilient integrated circuit which can be tuned to maximum performance. This can be achieved at a cost that is slightly higher than that of Semichrony RTL Sequential Optimizer. In comparison, asynchronous design achieves the same timing error resilience albeit at significantly higher cost in silicon area and timing performance.